
library ieee;

use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity sha_top_tb is
  
end entity;

architecture behav of sha_top_tb is

signal clk, rst, init : std_logic;
signal output_v : std_logic_vector(255 downto 0);
constant clk_period : time := 100 ns;

component sha_top is
  port(
    clk    : in std_logic;
    rst    : in std_logic;
    word   : in std_logic_vector(31 downto 0);
    finish : in std_logic;
    init   : in std_logic;
    setup  : in std_logic; -- To configure the mode
    mode   : in std_logic_vector(1 downto 0); -- "00": sha2-256, "11": sha2-512
    busy   : out std_logic;
    output_V : out std_logic_vector(255 downto 0)
  );
end component;

begin

clk_process:process
begin
clk <= '0';
wait for clk_period/2;

clk <= '1';
wait for clk_period/2;
end process;

rst_process:process
begin
rst <= '0';
init <= '0';
wait for 200ns;
rst <= '1';
init <= '1';
wait for 100ns;
init <= '0';
wait;
end process;

DUT: sha_top --entity work.sha_top
-- clk    : in std_logic;
-- rst    : in std_logic;
-- word   : in std_logic_vector(31 downto 0);
-- finish : in std_logic;
-- init   : in std_logic;
-- output_V : out std_logic_vector(255 downto 0)
port map(clk => clk,
         rst => rst,
         init => init,
         word => X"00000000",
         finish => '0',
         setup => '0',
         mode => "00",
         output_v => output_v);




end architecture;